In the world of modern microelectronics, the sheer computational ambition of artificial intelligence (AI), high-performance computing (HPC), and next-gen mobile platforms has finally rendered the traditional monolithic integrated circuit obsolete. We confront a stark reality: The Die is not enough.
This is where Advanced Packaging steps in, unlocking a massive, untapped source of system performance by revolutionizing the physical connections between chips. The industry has universally embraced heterogeneous integration–the assembly of diverse, specialized chiplets (Logic, Memory, I/O) into sophisticated Advanced Packages via 2.5D and 3D architectures. This transition elevates the package from mere housing to a critical system component.
In a world where nothing is constant, the placement and embedding processes cause chiplets to be randomly displaced and rotated, and the molded substrates to warp. The packaging world screams for a new hero which can cope with this alignment dilemma for fixed-template photolithography. A failure to compensate for these stochastic displacements means the package is essentially programmed to die. Enter the hero: Maskless Lithography – licensed to align.
Maskless systems digitally control pattern generation without the need of expensive, fixed masks. This allows dynamic corrections for the manufacturing imperfections inherent in large-area, multi-die packages. It offers the precision, flexibility, and cost efficiency needed to ensure that our stacked, heterogeneous packages don’t simply die in production, but instead live to compute another day.
To Die First or Die Last? Critical Fabrication Obstacles
The question facing every advanced packaging engineer is how to reliably integrate multiple chiplets with ultra-fine connections. The answer lies in mastering the fabrication of the Redistribution Layer (RDL)–the network of copper lines and vias connecting chiplets to each other and the external world.
Architectures like Fan-Out Wafer and Panel Level Packaging (FOWLP, FOPLP) epitomize this challenge. FOWLP generally follows two main strategies:
- Die-first (RDL-last): Pre-tested dies are embedded in a mold compound, and RDLs are built on top.
- RDL-first (Die-last): The interconnect layer is fabricated first, and dies are subsequently attached.
While each approach presents distinct trade-offs, a common challenge remains: Positional Distortion due to die shift or substrate warpage.
Die shift, introduced by the molding process, ensures that no two dies are precisely where they were designed to be for the subsequent lithography step. However, the RDL layer must align perfectly to the layer below and to the embedded dies. Additional warpage of the substrate is introduced by the different packaging materials and their varying shrinkage or thermal behavior.
At some point – when the misalignment becomes larger than RDL features itself – the lithography can fundamentally not be solved by a static photomask anymore. The only solution is adaptive lithography.
The Reticle Is Not Enough (to Cover the Chip)
Conventional stepper lithography relies on reticles, which impose a hard limit on the exposure area (typically ~26 mm × 33 mm). Modern heterogeneous packages, particularly those integrating complex processors with High-Bandwidth Memory (HBM), now frequently exceed this limit, pushing toward sizes of 85 mm x 85 mm or larger.
To use a stepper, manufacturers must use stitching techniques, which compromise yield and throughput. Maskless lithography, however, writes the pattern directly from digital data. It seamlessly covers large formats without stitching errors, regardless of the package size.
The Maskless Advantage: Adaptive Precision
Maskless lithography transforms these challenges from manufacturing bottlenecks into manageable process variables through four key capabilities:
- Adaptive Correction (Real-Time Compensation): Writing directly from digital data, maskless aligners can expose RDL layers that are custom-generated for each individual substrate. Geometric transformation algorithms compute a corrected exposure pattern that accurately compensates for die shift, rotation, and placement variation, using metrology data that maps the exact position and orientation of every chiplet.
- Mastering Warpage: Continuous autofocus tracking adjusts the laser focus across warped substrates, maintaining consistent resolution across the entire surface. This is critical for panel-level packaging where topographical variation can span tens of micrometers across a single substrate or panel.
- High Depth of Focus: The optical design enables the system to process non-planar substrates and accommodate thick photoresists while producing high-resolution features with large aspect ratios.
- Single-Substrate Customization: Without the need to produce a photomask, each substrate can receive a unique pattern (such as unique serialization or labeling) without slowing down production.
The MLA 300: A Production-Ready Solution
The MLA 300 Maskless Aligner delivers these advantages at production scale. Specifically engineered for the advanced packaging ecosystem, its 1.5 µm minimum feature size comfortably exceeds current RDL line/space requirements.
Designed for high-volume environments, the MLA 300 features full automation, customizable loading options, and seamless integration with Manufacturing Execution Systems (MES) to fit into existing workflows immediately.
Conclusion: Moore vs. Moore
For decades, performance was driven by the relentless shrinking of transistor sizes dictated by Gordon Moore. Today, the performance baton is passing to Advanced Packaging.
This new strategy is less about brute-force shrinking and more about sophisticated integration–reminiscent of Roger Moore’s interpretation of James Bond. It relies on combining specialized gadgets (chiplets) into a single, powerful system.
Maskless lithography is the essential gadget for this new era. It ensures that through flexible, real-time compensation and patterning beyond the reticle limit, complex packages do not die in fabrication, but Die Another Day–securing the next generation of high-performance computing.
